Defect Analysis for Advanced CMOS High-κ Gate Dielectric Stacks

The use new materials is required to sustain the continual shrinking of silicon devices. One set of materials, referred to as high-k gate dielectrics has been used. However its integration has been extremely difficult due the a lack on understanding of fixed charge within and charge transport though these materials. In recent work (see References 2,6,8 and conferences 4-6), a fuller understand of the nature and position of trapped or fixed charge arising form defects in these materials has been established. Techniques have been developed to not only measure the quality but also the position (on a nanometer scale) of these charges that so drastically affect device speed and performance. It is with an understanding of the electronic properties of these materials, as shown in this work, that can lead development and integration of such materials into standard CMOS processing.

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